Andrew J Farris

 

lordmorgul at gmail.com

 

Objective   Digital or Mixed Signal ASIC Physical Design Engineer

 

Education

      California Polytechnic State University San Luis Obispo

            M.S. Electrical Engineering, June 2008, GPA:  3.2/4.0

            B.S. Computer Engineering, June 2006, GPA:  3.51/4.0

 

Work Experience

      Research Assistant, Cal Poly, January 2007 – Present

            Conducted research project in lead-free solder reliability drop testing

            Coordinated team of multi-disciplinary undergraduate Honors students

            Presentation of reliability and failure analysis results to industry research partners

 

      Applications Engineer, Intern, Henkel Electronics, Irvine CA, July 2007 – September 2007

            Develop drop impact testing procedures for lead-free assemblies, JEDEC specifications

            Conducted drop impact reliability study using high-speed data acquisition system

 

      Research Assistant, Cal Poly, September 2005 – April 2006

            Hardware verification testing Cal PolyÕs NetPRL CiNIC version 3 network card

            PWB layout validation, board fabrication and assembly, fault testing and rework

 

      Web Applications Programmer, Mediastorm Design, December 2003 – May 2007

            Developed website back-ends for MySQL database, xhtml, xml data storage, debugging

            Secure handling of sensitive user data, financial transaction processing, forms processing

 

      Adventure Course Facilitator, The Oaks Christian Camp, June 2001 – August 2003

            Guided group activities in high-risk environment, safety and rescue procedures

 

      Waterfront Director, The Oaks Christian Camp, May 1998 – August 2003

            Managed six member staff, training, promoted from Head Lifeguard, LG/WSI certified

            Staffed / scheduled pool and lakeside activities including powerboat use, swim instructor

 

      Machinist, DS Precision Products, August 1998 – September 1999 (part time)

            Produced metal products to exacting standards, created tooling, maintained equipment

 

Skills

      ¥ VLSI integrated circuit layout   

      ¥ VHDL and schematic logic design

      ¥ CMOS, Dynamic, CPL digital logic

      ¥ SPICE simulation / analysis

      ¥ Cadence design tools, Electric, Magic

      ¥ Matlab, Minitab statistical analysis

      ¥ C++, Java, Python, PHP, Object Oriented

      ¥ C programming, debugging, gdb

      ¥ Linux / UNIX systems administration

      ¥ BASH shell scripting, SQL, Pascal, Fortran

      ¥ Digital Signal Processing, filtering

      ¥ Assembly language

 

Other Projects

      Designed and simulated 16-bit Kogge-Stone adder, 50nm process dynamic logic, IC layout

      Designed and simulated 32-bit register file with transistor wear-out aware iterative design

      Implemented six instruction single-cycle 32-bit MIPS processor at gate logic level

      Drafted patent application and intellectual property review for hand-held electronic device

      Contributor to open source software communities, Fedora Project Linux software tester

 

Affiliations

      Member, IEEE

      Member, SMTA

      Member, IMAPS

      Member, Cal Poly Linux Users Group (CPLUG)

 

Honors

      Dean's List, California Polytechnic State University, 2003

      Finalist, CSU Student Research Competition in Dominguez Hills, 2007

 

Publications

      A. Farris, J. Pan, A. Liddicoat, B. J. Toleno, D. Maslyk, D. Shangguan, J. Bath, D. Willie, D. A. Geiger, ÒDrop Test Reliability of Lead-free Chip Scale PackagesÓ, Proceedings of 2008 IEEE ECTC, pp. 1173-1180.